Many arrangements have been proposed for testing combinational logic circuits, such as are included on circuit boards and chips, for permanent faults such as a grounded point or an open circuit. These permanent faults are often referred to as "stuck-at" faults.
However, even though a circuit board or a chip does not have any "stuck-at", or permanent faults, it may still not perform accurately when put in service. Thus a logic circuit might be expected to operate correctly during successive "clock" periods of operation of the data circuitry, which may be measured in millionths of a second (micro-seconds) or in billionths of a second (nanoseconds); and in fact, the switching time for the logic circuitry might take more than one clock period, so that a timely and correct output is not obtained. When a circuit response requires more time than specified by the design requirements, the circuit is said to contain a delay fault. Delay testing can be used to detect delay faults.
Some delay testing is often accomplished immediately following circuit fabrication, with special equipment available only at the manufacturing facility. However, delay faults often arise at later points in time, and effective detection of such faults has presented a significant problem, particularly as the complexity and density of digital logic circuits has increased.
The motivation behind delay testing is to ensure that the circuit will run at a pre-established rate. Usually no attempt is made to check for the delay faults in the LSI circuit once it has been put into functional operation, and whatever maintenance tests or self-tests that are provided usually deal only with "stuck-at" faults With the adoption of VLSI and increasing integration densities, there is a reasonable probability that delay faults may arise in a circuit during the operational phase. This may well be due to physical changes, such as metal migration, which in turn may result in the variation of current and voltage distributions within the circuit, thereby affecting its dynamic behavior by causing the logic to switch at slower speeds as compared to the specified normal values. These delay faults may well be the first phase of circuit degradation, and are often invisible to the maintenance self tests. They often appear to a maintenance engineer as intermittent faults and are extremely difficult to diagnose.